By Jose Moreira
Offering a whole advent to the state of the art in high-speed electronic checking out with computerized try gear (ATE), this sensible source is the 1st ebook to concentration completely in this more and more vital subject. that includes transparent examples, this one-stop reference covers all severe elements of the topic, from high-speed electronic fundamentals, ATE instrumentation for electronic functions, and attempt and measurements, to creation checking out, help instrumentation and textual content fixture layout.
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Extra resources for An Engineer's Guide to Automated Testing of High-Speed Interfaces
1 Jitter Histogram The jitter histogram is one of the most commonly used ways of analyzing the jitter of a digital signal. The idea is to measure the time interval error of each edge of the signal and generate a histogram of the measurements. The exact way the measurement array of values required for the histogram is generated depends on the specifics of the measurement methodology and instrument (to be discussed with more detail in Chapter 5). Typically an array of values for the measured jitter at each transition is generated.
4). 4), we will also use it through this book, although the reader should be aware of this possible distinction. 22 An Engineer’s Guide to Automated Testing of High-Speed Interfaces dependency. In the figure, the noise of the receiver moves some of the strobing edges to wrong positions that might generate bit errors. The measurement setup uses a 10-bit pattern to compute the BER of the system. 2. 18 Simplistic example showing how the measured BER can be different from the “real BER” due to the used pattern.
18 Simplistic example showing how the measured BER can be different from the “real BER” due to the used pattern. For measuring a DUT BER, one needs to be able to transmit bits to the DUT, find out if the transmitted bit was correctly received by the DUT, receive bits from the DUT, and find out if the received bits correspond to the intended bits to be transmitted by the DUT. 19 shows a block diagram of two possible measurement setups. 19 Block diagram of bit error rate measurement setup for a digital I/O cell in a DUT (left: The DUT I/O cell can be programmed to a loopback mode; right: the data must be obtained after the internal logic of the device in some lower speed pins).
An Engineer's Guide to Automated Testing of High-Speed Interfaces by Jose Moreira